Mon Mar 03 17:15:12 UTC 2025: ## IIT Madras Hosts Second Digital India RISC-V Symposium
**Chennai, March 3, 2025** – The Indian Institute of Technology Madras (IIT-M) is hosting the second Digital India RISC-V (DIR-V) symposium, a two-day event inaugurated Sunday. The symposium aims to bolster India’s presence in the global semiconductor landscape, a goal highlighted by former Union Minister of State Rajeev Chandrasekhar.
IIT-M, a leader in RISC-V research and development, has spearheaded the creation of India’s first indigenous RISC-V based processor ecosystem, the Shakti family of processors. The institute is collaborating with the Ministry of Electronics and Information Technology (MeitY) and RISC-V International to organize this significant event.
The symposium features discussions on India’s semiconductor roadmap, advancements in RISC-V processor design, and open-source hardware innovations. Attendees include experts from around the globe, policymakers, startups, academics, and industry leaders. RISC-V International, a non-profit organization with over 4,200 members from 70 countries, is actively involved.
IIT-M director V. Kamakoti emphasized the symposium’s role in bringing together designers, chip architects, and product and application OEMs onto a single platform. He highlighted the importance of developing a complete microprocessor ecosystem within India, noting that the country has historically lagged in semiconductors and electronics. Kamakoti expressed optimism that India can now leverage its strengths to lead in the next wave of technological advancement, particularly with RISC-ISA and the DIR-V program.
Chandrasekhar, credited with coining the term “Digital India RISC-V,” expressed hope that the DIR-V ecosystem will yield significant commercial success and practical applications.
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